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this x24c02 device has been acquired by ic microsystems sdn bhd from xicor, inc. 1 2k x24c02 256 x 8 bit serial e 2 prom ? xicor, 1991 patents pending characteristics subject to change without notice description the x24c02 is cmos a 2048 bit serial e 2 prom, internally organized 256 x 8. the x24c02 features a serial interface and software protocol allowing operation on a simple two wire bus. three address inputs allow up to eight devices to share a common two wire bus. xicor e 2 proms are designed and tested for applica tions requiring extended endurance. inherent data retention is greater than 100 years. available in d ip, msop and soic packages. features ? 2.7v to 5.5v power supply ? low power cmos ? active current less than 1 ma ?standby current less than 50 a ? internally organized 256 x 8 ? self timed write cycle ? typical write cycle time of 5 ms ? 2 wire serial interface ? bidirectional data transfer protocol ? four byte page write operation ? minimizes total write time per byte ? high reliability ? endurance: 10 0,000 cycles ?data retention: 100 years ? new hardwire?write control function functional diagram 3838 fhd f01 start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 64 x 32 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl (3) a 2 (2) a 1 (1) a 0 d out load inc ck 8 (7) wc 3838-1.2 7/30/96 t0/c3/d1 sh ic mic ic microsystems tm
x24c02 2 pin configuration pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data in to and out of the device. it is an open drain output and may b e wire -ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to th e guide- lines for calculating typical values of bus pull-up resistors graph. address (a 0 , a 1 , a 2 ) the address inputs are used to set the least signif icant three bits of the seven bit slave address. these in puts can be static or actively driven. if used staticall y they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven to v ss or to v cc . write control (wc) the write control input controls the ability to wri te to the device. when wc is low (tied to v ss ) the x24c02 will be enabled to perform write operations. when wc is high (tied to v cc ) the internal high voltage circuitry will be disabled and all writes will be disabled. 3838 fhd f02 pin descriptions symbol description a 0 ?a 2 address inputs sda serial data scl serial clock wc write control v ss ground v cc +5v 3838 pgm t01 a 0 a 1 a 2 v ss 1 2 3 4 8 7 6 5 v cc wc scl sda x24c02 dip/soic/msop
x24c02 3 figure 1. data validity scl sda data stable data change 3838 fhd f06 device operation the x24c02 supports a bidirectional bus oriented pr otocol the protocol defines any device that sends data ont o the bus as a transmitter and the receiving device as th e receiver . the device controlling the transfer is a mast er and the device being controlled is the slave. the master wi ll always initiate data transfers and provide the clock for b oth transmit and receive operations. therefore, the x24c02 wi ll be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are re- served for indicating start and stop conditions. re fer to figures 1 and 2. start condition all commands are preceded by the start condi tion, which is a high to low transition of sda when scl i s high. the x24c02 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met.
x24c02 4 stop condition all communications must be terminated by a stop con dition , which is a low to high transition of sda when scl is high. the stop condition is also used by the x24c02 to place the device in the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indica te successful data transfer. the transmitting device, either master or slave, will release the bus after transmi tting eight bits. during the ninth clock cycle the receiv er will pull the sda line low to acknowledge that it receiv ed the eight bits of data. refer to figure 3. the x24c02 will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write operation have been selected, the x24c02 will respond with an acknowled ge after the receipt of each subsequent eight bit word . in the read mode the x24c02 wil l transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the x24c02 will continue to transmit data. if an acknowledge i s not detected, the x24c02 will terminate further data tr ans- missions. the master must then issue a stop conditi on to return the x24c02 to the standby power mode and place the device into a known state. figure 2. definition of start and stop scl sda start bit stop bit figure 3. acknowledge response from receiver scl from master data output from transmitter 1 8 9 data output from receiver start acknowledge 3838 fhd f07 3838 fhd f08
x24c02 5 device addressing following a start condition the master must output the address of the slave it is accessing. the most sign ificant four bits of the slave are the device type identifi er (see figure 4). for the x24c02 this is fixed as 10 10[b]. the next three significant bits address a pa rticular device. a system could have up to eight x24c02 devices on the bus (see figure 10). the eight addresses are define d by the state of the a 0 , a 1 and a 2 inputs. the last bit of the slave address defines the opera tion to be performed. when set to one a read operation is selected, when set to zero a write operations is se lected. figure 4. slave address following the start condition, the x24c02 monitors the sda bus comparing the slave address being transmitt ed with its slave address (device type and state of a 0 , a 1 and a 2 inputs). upon a correct compare the x24c02 outputs an acknowledge on the sda line. depending on the state of the r/w bit, the x24c02 will execute a read or write operation. write operations byte write for a write operation, the x24c02 requires a second address field. this address field is the word addre ss, comprised of eight bits, providing access to any on e of the 256 words of memory. upon receipt of the wo rd address the x24c02 responds with an acknowledge, an d awaits the next eight bits of data, again respondin g with an acknowledge. the master then terminates the transfer by generating a stop condition, at which t ime the x24c02 begins the internal write cycle to the nonvo latile memory. while the internal write cycle is in progre ss the x24c02 inputs are disabled, and the device will not respond to any requests from the master. ref er to figure 5 for the address, acknowledge and data tran sfer sequence. 1 0 1 0 a2 a1 a0 r/w device type identifier device address figure 6. page write f igure 5. byte write bus activity: master sda line bus activity: x24c02 s t a r t slave address s s t o p p a c k a c k a c k word address data 3838 fhd f010 3838 fhd f011 3838 fhd f09 bus activity: master sda line bus activity: x24c02 s t a r t slave address s s t o p p a c k a c k a c k a c k a c k word address (n) data n data n+1 data n+3 note: in this example n = xxxx 000 (b); x = 1 or 0
x24c02 6 page write the x24c02 is capable of a four byte page write ope ration. it is initiated in the same manner as the byte wri te operation, but instead of terminating the write cyc le after the first data word is transferred, the master can transmit up to three more words. after the receipt of each w ord, the x24c02 will respond with an acknowledge. after the receipt of each word, the two low order a ddress bits are internally incremented by one. the high or der six bits of the address remain constant. if the master should transmit more than four words prior to generating t he stop condition, the address counter will ?roll over? and the previously written data will be overwritten. as wit h the byte write operation, all inputs are disabled unti l completion of the internal write cycle. refer to figure 6 for the address acknowledge and data transfer sequence. acknowledge polling the disabling of the inputs, during the inte rnal write operation, can be used to take advantage of the typ ical 5 ms write cycle time. once the stop condition is i ssued to indicate the end of the host?s write ope ration the x24c02 initiates the internal write cycle. ack poll ing can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the x24c02 is still busy with the write operation no ack will be returned. if the x24c02 ha s completed the write operation an ack will be return ed and the master can then proceed with the next read or write operation. read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address is set to a one. there are three basi c read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of th e read operation is not a ?don?t care.? to terminat e a read operation, the master must either issue a stop cond ition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no flow 1. ack polling sequence 3838 fhd f12
x24c02 7 current address read internally the x24c02 contains an address counter t hat maintains the address of the last word acces sed, incremented by one. therefore, if the last access ( either a read or write) was to address n, the next read o peration would access data from address n + 1. upon receipt of the slave address with the r/w bit set to one, the x24c02 issues an acknowledge and transmits the eigh t bit word during the next eight clock cycles. the master terminates this transmission by issuing a stop cond ition, omitting the ninth clock cycle acknowledge. r efer to figure 7 for the sequence of address, acknowledge a nd data transfer. figure 7. current address read bus activity: master sda line bus activity: x24c02 s t a r t slave address s s t o p p a c k data figure 8. random read 3838 fhd f13 3838 fhd f14 random read random read operations allow the master to access a ny memory location in a random manner. prior to issuin g the slave address with the r/w bit set to one, the master must first perform a ?dummy? write operation. the m aster ter issues the start condition, and the slav e address followed by the word address it is to read. after t he word address acknowledge, the master immediately reissue s the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the x24c02 and then by the eight bit word. the mast er terminates this transmission by issuing a stop cond ition, omitting the ninth clock cycle acknowledge. r efer to figure 8 for the address, acknowledge and data tran sfer sequence. bus activity: master sda line bus activity: x24c02 s t a r t slave address s s t o p p a c k a c k a c k word address n slave address data n s t a r t s
x24c02 8 sequential read sequential read can be initiated as either a current address read or random access read. the first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24c02 continues to o utput data for each acknowledge received. the master terminates this transmission by issuing a stop cond ition, omitting the ninth clock cycle acknowledge. figure 9. sequential read figure 10. typical system configuration master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl v cc bus activity: master sda line bus activity: x24c02 slave address a c k a c k data n+x s t o p p data n a c k data n+1 a c k data n+2 3838 fhd f15 3838 fhd f16 the data output is sequential, with the data from a ddress and followed by the data from n + 1. the address co unter for read operations increments all address bits, al lowing the entire memory contents to be serially read during one operation. at the end of the address space (add ress 255), the counter ?rolls over? to address 0 and t he x24c02 continues to output data for each acknowledg e received. refer to figure 9 for the address, acknow l edge and data transfer sequence.
x24c02 9 absolute maximum ratings* temperature under bias .................. ?65 c to +135 c storage temperature ....................... ?65 c to +150 c voltage on any pin with respect to v ss ................................ ?1.0v to +7.0v d.c. output current ............................... ............. 5 ma lead temperature (soldering, 10 seconds) ..... 300 c *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and the functional ope ration of the device at these or any other conditions above t hose indicated in the operational sections of this speci fication is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. supply voltage limits x24c02 4.5v to 5.5v x24c02-3.5 3.5v to 5.5v x24c02-3 3v to 5.5v x24c02-2.7 2.7 to 5.5v 3838 pgm t10 recommended operating conditions temperature min. max. commercial 0 c 70 c industrial ?40 c +85 c military ?55 c +125 c 3838 pgm t09 d.c. operating characteristics (over recommended operating conditions unless other wise specified). limits symbol parameter min. max. units test conditions l cc1 power supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open, all other l cc2 power supply current (write) 2 inputs = gnd or v cc ? 0.3v i sb (1) standby current 50 a scl = sda = v cc ? 0.3v, all other inputs = gnd or v cc , v cc = 5.5v i sb (2) standby current 30 a scl = sda = v cc ? 0.3v, all other inputs = gnd or v cc = 3.3v + 10% i li input leakage current 10 a v in = gnd to v cc i lo output leakage current 10 a v out = gnd to v cc v ll (2) input low voltage ?1.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3 ma 3838 pgm t02 capacitance t a = 25 c, f = 1 mhz, v cc = 5v symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a 0 , a 1 , a 2 , scl, wc) 6 pf v in = 0v 3838 pgm t04 notes: (1)must perform a stop command prior to measurement . (2)v il min. and v ih max. are for reference only and are not tested. (3 )this parameter is periodically sampled and not 100% test ed.
x24c02 10 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input and output timing levels v cc x 0.5 3838 pgm t05 equivalent a.c. load circuit 1533 output 100pf 5.0v 3838 fhd f18 a.c. characteristics (over recommended operating conditions) data input timing symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time 100 ns constant at scl, sda inputs t aa scl low to sda data out valid 0.3 3.5 s t buf time the bus must be free before a 4.7 s new transmission can start t hd:sta start condition hold time 4.0 s t low clock low period 4.7 s t high clock high period 4.0 s t su:sta start condition setup time 4.7 s t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 s t dh data out hold time 300 ns 3838 pgm t06 bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 3838 fhd f04 power - up timing symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms 3838 pgm t07 notes: (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initia ted. these parameters are periodically sampled and not 100% tested.
x24c02 11 guidelines for calculating typical values of bus pull-up resistors symbol table must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance outputs inputs waveform 120 100 80 40 60 20 20 40 60 80100120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k 3838 fhd f17 write cycle limits symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms 3838 pgm t08 the write cycle time is the time from a valid stop condition of a write sequence to the end of the int ernal erase/program cycle. during the write cycle, the x24c02 bus interface circuits are disabled, sda is allowed to remain high, and t he device does not respond to its slave address. write cycle timing 3838 fhd f05 scl sda 8th bit word n ack t wr stop condition start condition x24c02 address notes: (5)typical values are for t a = 25 c and nominal supply voltage (5v) (6) t wr is the minimum cycle time from the system perspect ive when polling techniques are not used. it is the maximum time the device requires to perform the internal write opera tion. resistance (k )
x24c02 12 packaging information 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.140 (3.56) 0.130 (3.30) 0.020 (0.51) 0.015 (0.38) pin 1 seating plane 0.062 (1.57) 0.058 (1.47) 0.255 (6.47) 0.245 (6.22) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8 - lead plastic dual in - line package type p note: all dimensions in inches (in parentheses in m illimeters) 0.092 (2.34) dia. nom. half shoulder width on all end pins optional 0.015 (0.38) max.
x24c02 13 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.027 (0.683) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 8 - lead plastic small outline gull wing package type s note: all dimensions in inches (in parenthesis in m illimeters)
x24c02 14 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8 - lead miniature small outline gull wing package type m not e: 1. all dimensions in inches and (millimeters) 3003 ill 01 packaging information
x24c02 15 notes
x24c02 16 x24c02 p t g - v g = rohs compliant lead free packge blank = standard package. non lead free device ordering information v cc limits blank = 4.5v to 5.5v 3.5 = 3.5v to 5.5v 3 = 3.0v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?40 c to +85 c m = military = ?55 c to +125 c package p = 8-lead plastic dip s8 = 8-lead soic m = 8-lead msop limited warranty devices sold by xicor, inc. are covered by the warranty and p atent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding t he information set forth herein or regarding the fre edom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness for any purpose. x icor, inc. reserves the right to discontinue production an d change spe cifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circ uitry other than circuitry embodied in a xicor, inc. prod uct. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the followin g u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,3 14,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,7 06; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4, 874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may en danger life, system designers using this product should desi gn the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical co mponents in life support devices or systems. 1. life support devices or systems are devices or systems which, ( a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance wit h instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life suppor t device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. blank = 8-lead soic p = 8-lead plastic dip s8 = 8-lead soic m = 8-lead msop g= rohs compliant lead free blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?40 c to +85 c m = 4.5v to 5.5v, ?55 c to 125 c b = 3.5v to 5.5v, 0 c to +70 c c = 3.5v to 5.5v, ?40 c to +85 c d = 3.0v to 5.5v, 0 c to +70 c e = 3.0v to 5.5v, ?40 c to +85 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?40 c to +85 c part mark convention x24c02 x g x

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